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The purpose of irqbalance is to distribute interrupts
accross cpus in an smp system such that cache-domain
affinity is maximized for each irq. In other words,
irqbalance tries to assign irqs to cpu cores such that each
irq stands a greater chance of having its interrupt handler
be in cache when the irq is asserted to the cpu. This raises
a few interesting cases in which the behavior of irqbalance
may be non-intuitive. Most notably, cases in which a system
has only one cache domain. Nominally these systems are only
single cpu environments, but can also be found in multi-core
environments in which the cores share an L2 cache. In these
situations irqbalance will exit immediately, since there is
no work that irqbalance can do which will improve interrupt
handling performance. This is normal and not cause for
concern. For more information regarding irqbalance, please
visit http://irqbalance.org/
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